1. Field of the Invention
The present invention relates to a semiconductor storage device including a plurality of interconnection layers which are connected by contact hole interconnections.
2. Background Art
In recent years, demands for small-sized large-capacity non-volatile semiconductor storage devices have increased rapidly. Among them, NAND flash memories which can be anticipated to have higher integration and larger capacities as compared with conventional NOR flash memories are attracting attention. The width and spacing (line and space) of interconnections in non-volatile semiconductor storage devices such as NAND flash memories are shrunk as the fine resolution technique advances.
In general, in non-volatile semiconductor memories, it is necessary to form contacts which electrically connect upper layer interconnections to the lower layer interconnections in areas where word lines and bit lines of memory cells make contact with a memory cell array and are pulled out to a peripheral circuit part. In general, it is more difficult to form contact holes by using photolithography than to form interconnections (see, for example, Japanese Patent Laid-Open No. 2004-348118).
Furthermore, in the conventional art, the memory cell array shrunk in size and the peripheral circuit having comparatively large patterns are subjected to exposure lighting together and processed.
As the size shrinking of the non-volatile semiconductor memory is advanced, the lithography margin and processing margin cannot be ensured, and consequently it is not possible to conduct exposure and processing on the memory cell array and the peripheral circuit collectively. Therefore, the double exposure technique and the double processing technique which use two photomasks on the same layer are used.
In addition, for period ends of the line and space, contacts of the bit lines and contacts of the source lines, a more complicated pattern arrangement or the Sub-Resolution Assist Feature (Sraf) arrangement functioning as a dummy pattern of reticles becomes necessary (see, for example, Japanese Patent Laid-Open No. 2008-66586). They exert a direct influence upon the increase of cost.
Furthermore, for example, the side wall processing technique is adopted to form the memory cell array. Therefore, the minimum exposure pitch of the element area, the word lines and the bit lines becomes twice the minimum processing pitch (see, for example, Japanese Patent Laid-Open No. 2008-27978). Therefore, the minimum size at the time of exposure becomes equal to, for example, the size of contact holes connected to the bit lines.
Especially if the side wall processing technique is adopted for interconnections of sense amplifiers which are denser in layout pattern than the peripheral circuit, pattern variations of contact holes connected to the interconnections increase. In this case, the difficulty of the exposure rises.
Furthermore, in the conventional art, the contact holes connected to the interconnections of the sense amplifiers have, for example, a pattern in which two contact holes are arranged in the bit line direction, and several Sraf's are associated in the word line direction. In the bit line direction as well, Sraf's are associated with between contact holes and above and below the contact holes.
Because of size shrinking and introduction of the side wall processing technique, however, the lithography margin is liable to become narrow for the contact holes connected to the interconnections of the sense amplifiers.